About us
Who's behind the screen?
Key team players are Mohan Harihara, MS in Computer Engineering, and Dr. Chithra Rajagopalan, PhD in Electrical Engineering. They lead turnkey projects from start to finish, focusing on augmenting the existing DV team with the verification of large designs. Their proficiency includes the architecting and development of a UVM testbench to ensure high-quality outcomes. You now have a one stop shop for all your verification needs. The team also includes three other top notch DV engineers.
What is verifxpress?
VerifXpress is Apna's specialized tool that produces a robust and self-checking UVM testbench for a DUT. The tool needs details of the interface, timing protocol, micro-architecture details of the DUT. The tool has successfully produced complete UVM testbench solutions for L2cache, L3cache, a complicated Flit-based Mesh network, LiDar ASIC, and Soundwire-based RTL blocks. Additionally, it generates tests, interface agents (VIPs), sequence libraries, a prediction model, and checkers. With a focus on best practices, the tool produces UVM code that meets industry standards. While the prediction model and checkers may require some fine-tuning and oversight as the design is better understood, VerifXpress remains an essential asset for UVM testbench architect and development.
Verifxpress: no bugs left behind
more about the product
In less than two weeks, VerifXpress delivers a fully self-checking UVM testbench. Given a detailed micro-architecture spec of the DUT, Apna team is able to extract needed information and create specs that are input to VerifXpress. Various specs are created that help in the VIP generation, Scoreboard & Checkers, Sequence libraries, basic tests, functional coverage model, regression lists, RAL models for registers, Makefile based scripts for Questa, Xcelium and VCS. The UVM testbench produced is correct by construction and has all the best practices of UVM and verification concepts built in. End of test checks, error reporting, assertions for protocol violations, checks for all RTL outputs, interrupt handling, RAL based UVM POR, bitbash tests.
how it can save you time and money
All agents (VIP) produce "tracker.log" file that displays what is seen on the interfaces, a very useful and powerful debugging help. There are no limits to the number of UVM testbenches that VerifXpress can develop, making it a powerful tool for building bottom's up verification testbenches. Block level testbenches can be reused at the higher level of testbenches (cluster, full chip). SInce a complete testbench is produced, checkers are enabled from the first day of deployment, regression list makes is easy to manage overall progress and tracking, presence of functional coverage from day-1 is a big bonus for any DV team - imagine having the infrastructure to collect functional coverage from day-1? DV manager's dream!!
past clients: stealth mode startup companies
From start to finish, VerifXpress provided comprehensive testbenches for the full LiDar based chip. Several module-level UVM testbenches, sub-chip testbenches, and full bench testbenches were produced, showcasing the full capabilities of VerifXpress and Apna's expertise.
Soundwire based RTL module was fully verified by the UVM testbench developed by VerifXpress. Prediction model, Soundwire bustracker, checkers for COMMAND, DATA.
Fully self checking UVM testbench for an L2Cache and L3Cache for a RISC-v based processor at a stealth mode startup using proprietary bus protocol was developed using VerifXpress. Proprietary protocol VIP developed by VerifXpress.
past clients: simple machines inc.
The verification of three complex blocks was completed using VerifXpress - a) L2Cache b) Flit based network-mesh c) Proprietary secret sauce block. Several dozen bugs found on all the three blocks. The speed, precision and correct by construction testbench was marveled by the company and Apna still hears great things from managers!!
To sum it up...
You are in great reliable hands working with Apna. We collaborate closely with your company's architects, software teams and designers, ensuring that our chip verification services are top-notch and that the UVM testbench created is both stellar and bug-free! Our expertise in UVM, all aspects of verification guarantees that every aspect of your product is meticulously verified to perfection and being bug-free!! Apna periodically reviews testplans and testbench code with the team. Apna is always open for suggestions and incorporate all feedback in a timely fashion.